1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to an embedded bit line structure, a field effect transistor (FET) structure with the same and a method of fabricating the same.
2. Description of the Prior Art
A vertical Fin-shaped gate field effect transistor (FinFET) with an embedded (or buried) bit line is the mainstream to achieve next generation 4F2 (feature) cell because of simplified middle-of-line (MOL) process. However, front-end-of-line (FEOL) process becomes more complicated accordingly. Especially, shallow trench isolation (STI) with half feature size is required. As a result, an aspect ratio of STI larger than 20 happens for thirties nm generation, and difficulty for gap fill with oxide film could be an obstacle to dynamic random access memory (DRAM) shrinkage.
Vertical surrounding gate transistors (SGT) with embedded bit lines have been proposed with enlarging isolation rule (close to 1F (feature)) to greatly reduce STI manufacturing difficulty. However, Vth (threshold voltage) stability for the memory cell array becomes much worse because of complicated fabricating process, including, for example, tedious embedded bit line formation steps, recess for spin-on-dielectric (SOD) formation steps, metal and n+ type poly defined transistor gate length. Reducing Vth variation with longer channel length is also unfeasible under vertical dimension constraint.
Therefore, there is still a need for a novel FinFET structure and the fabrication process therefore to avoid the aforesaid problems.